# FPGA Engineer - Company: [Difflogic]() - Location: Santa Clara - Team: R&D - Employment type: Full Time - Posted: February 23, 2026 ## Job description DiffLogic is on a mission to end matrix multiplication. We don't run models on chips. We build chips that *are* the model. That means tape-out isn't a milestone. It's the product. We iterate fast, we tape out frequently, and every spin ships smarter silicon than the last. We're hiring exceptional FPGA engineers, with extensive experience in low-latency applications and Video IP. *You'll work on questions that don't yet have established solutions, and most have never been asked outside this lab*. And you will *not* simply redevelop yet another variation of existing solutions. Everyone here is hands-on and moves fast. If you also have ASIC tape-out experience, please indicate it, and apply to "ASIC / Physical Design Engineer”. ## Apply [Apply on Difflogic]() Canonical job page: